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1 characteristics subject to change without notice 2083 1.1 06/04/04 sms46 summit microelectronics, inc. ?summit microelectronics, inc., 2004 ? 1717 fox dr. san jose, ca 95131 phone 408-436-9890 fax 408-436-9897 www.summitmicro.com preliminary information 1 (see last page) z z z z z operational from any of four voltage monitoring inputs z z z z z four independent programmable reset outputs z z z z z programmability allows monitoring any voltage between 0.6v and 5.6v with no external components z z z z z programmable 5mv steps in the low range z z z z z programmable watchdog timer z z z z z programmable reset pulse width z z z z z fault status register z z z z z 4k-bit nonvolatile general purpose memory applications z z z z z desktop/notebook/tablet computers z z z z z multi-voltage systems z z z z z telecom/network servers z z z z z portable battery-powered equipment z z z z z set-top boxes z z z z z data-storage equipment quad programmable precision supervisory controller with independent resets and 4k-bit nonvolatile memory features introduction the sms46 is a highly programmable voltage supply controller and supervisory circuit designed specifically for advanced systems that need to monitor multiple voltages. the sms46 can monitor four separate voltages without the need of any external voltage divider circuitry. this allevi- ates the need for factory-trimmed threshold voltages and the use of external components to accommodate different supply voltages and tolerances. the sms46 has four programmable independant reset outputs to control different devices for varying reset condi- tions such as uv, ov, watchdog and user pushbutton applications. the sms46 watchdog timer has a user programmable time-out period and it can be placed in an idle mode for system initialization or system debug. all of the functions are user accessible through an industry standard i 2 c serial interface. programming of configuration, control and calibration val- ues by the user is simplified with the smx3200 interface adapter and windows gui software obtainable from sum- mit microelectronics. simplified application drawing figure 1 - precision quad power supply monitor can monitor any voltage over the range of 0.6v to 5.6v. one of the four supplies must be above 2.7v to power the sms46. v 0 v 1 v 2 v 3 reset#0 reset#3 vdd_cap reset#1 reset#2 i 2 c 3.3v 2.5v 1.8v 1.2v sms46 a2 a1 sda scl 7 6 9 10 1 16 2 3 14 mr# monitored supplies 15 wldi gnd 8 13 12 11 5 4 0.1f vpullup (0 to +12v) up/dsp asic/fpga logic lcd from up reset#
2 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information functional block diagram + ? ref nv dac + ? ref nv dac + ? ref nv dac + ? ref nv dac v 0 16 v 1 2 v 2 3 v 3 14 mr# 1 programmable watchdog timer serial bus control logic 4k-bit nv memory reset#0 11 sda vdd_cap wldi 9 15 10 scl a2 7 6 a1 configuration register gnd 8 vdd_cap 50k ? 50k ? 12 supply arbitration v 3 v 2 v 1 v 0 vdd_cap reset#1 4 reset#2 5 reset#3 13 programmable reset pulse generator
3 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information pin configuration pin names mr# v 1 v 2 r eset#1 r eset#2 a1 a2 gnd v 0 wldi v 3 reset# 3 vdd_ca p reset# 0 scl sda 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n i pe m a nn o i t c n u f 1# r mt u p n i t e s e r l a u n a m 2v 1 r o t i n o m d n a y l p p u s e g a t l o v t u p n i 3v 2 r o t i n o m d n a y l p p u s e g a t l o v t u p n i 41 # t e s e rt u p t u o 1 # t e s e r 52 # t e s e rt u p t u o 2 # t e s e r 61 at u p n i s s e r d d a 72 at u p n i s s e r d d a 8d n gn r u t e r y l p p u s r e w o p 9a d so / i a t a d l a i r e s 0 1l c sk c o l c a t a d l a i r e s 1 10 # t e s e rt u p t u o 0 # t e s e r 2 1p a c _ d d vt u p t u o y l p p u s r e w o p 3 13 # t e s e rt u p t u o 3 # t e s e r 4 1v 3 r o t i n o m d n a y l p p u s e g a t l o v t u p n i 5 1i d l wt p u r r e t n i r e m i t g o d h c t a w 6 1v 0 r o t i n o m d n a y l p p u s e g a t l o v t u p n i
4 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information dc operating characteristics ( over recommended operating conditions; voltages are relative to gnd ) l o b m y sr e t e m a r a ps e t o n. n i m. p y t. x a mt i n u d d ve g a t l o v y l p p u s g n i t a r e p o - t u o t e s e r d i l a v a o t s r e f e r . n i m v 1 d e t a r e n e g g n i e b t u p 0 . 15 . 5v t a : s n o i t a r e p o e t i r w / d a e r y r o m e m t a e b t s u m s t u p n i v e h t f o e n o t s a e l . n i m d d v e v o b a r o 7 . 25 . 5v d d it n e r r u c y l p p u s d d v v ; v 5 . 5 0 v ; v 7 . 4 t n i o p p i r t 1 v , 2 , v 3 s t u p t u o l l a ; d d v = # r m ; d n g = g n i t a o l f 0 0 20 0 4a y r o m e m r o r e t s i g e r n o i t a r u g i f n o c s s e c c a 3a m v h t p e g n a r d l o h s e r h t e l b a m m a r g o r p ) e g n a r w o l ( v e g n a r e g a t l o v d l o h s e r h t t e s e r 0 o t v 3 ) s t n e m e r c n i v m 5 ( 6 . 05 7 8 . 1v v h t p e g n a r d l o h s e r h t e l b a m m a r g o r p ) e g n a r h g i h ( v e g n a r e g a t l o v d l o h s e r h t t e s e r 0 o t v 3 ) s t n e m e r c n i v m 5 1 ( 8 . 15 2 6 . 5v v c c a h t p d l o h s e r h t e l b a m m a r g o r p y c a r u c c a v h t p d l o h s e r h t d e m m a r g o r p e h t s i v e h t n i h t i w t n i o p t e s h t p e g n a r 0 . 1 ?v h t p 0 . 1% v t s y h v t s r s i s e r e t s y hw o l e b 1 e t o n e e sd b tv m r u p e c n a t s i s e r p u - l l u ps n i p i d l w d n a # r m0 5k ? v l o t u p t u o e g a t l o v w o l i k n i s v , a m 1 = p a c _ d d v v 7 . 23 . 0v i k n i s v , a 0 0 2 = p a c _ d d v v 0 . 1 =3 . 0v v l i d l o h s e r h t t u p n i 6 . 0v v h i 7 . 0 v d d v * note - stresses beyond the listed absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. temperature under bias ........................ ?55c to 125c storage temperature ............................. ?65c to 150c lead solder temperature (10s) ........................... 300 c terminal voltage with respect to gnd: v 0 , v 1 , v 2 , and v 3 ......... ?0.3v to 6.0v reset#0-3 ..................... ?0.3v to 15v all others ....................... ?0.3v to 6.0v junction temperature.......................??.....?...150c esd rating per jedec????????..?.?..2000v latch-up testing per jedec???..??.......?100ma absolute maximum ratings* recommended operating conditions industrial temperature range............... ?40 o c to +85 o c. commercial temperature range..............?5 o c to +70 o c. v supply supply voltage............................2.7v to 5.5v v supply = device supply voltage provided by the highest v x input. package thermal resistance ( ja) 16 lead ssop????????.????.?23 o c/w moisture classification level 1 (msl 1) per j-std- 020 reliability characteristics data retention???????.????..?..100 years endurance?????????.?..??.100,000 cycles note 1: low range hysteresis = 4.2 x (vtrip - 0.5 volts) mv. for vtrip = 1.0 volts, hysteresis = 2.1 mv (0.21 %), high range hysteresis = 12.6 x (vtrip -0.5 volts) mv. for vtrip = 5.0 volts, hysteresis = 56.7 mv (1.13%).
5 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information l o b m y sr e t e m a r a ps e t o n. n i m. p y t. x a mt i n u t o t r p e s l u p t e s e r e l b a m m a r g o r p h t d i w 9 15 21 3s m 8 30 53 6s m 5 70 0 15 2 1s m 0 5 10 0 20 5 2s m t t s r d y a l e d # t e s e r o t n i ve v i r d r e v o v m 0 0 10 2s t o t d w p g o d h c t a w e l b a m m a r g o r p d o i r e p r e m i t f f o? 0 0 30 0 40 0 5s m 0 0 60 0 80 0 0 1s m 0 0 2 10 0 6 10 0 0 2s m 0 0 4 20 0 2 30 0 0 4 0 0 8 40 0 4 60 0 0 8s m t r m h t d i w e s l u p t u p n i # r m g n i r b o t d e r i u q e r e s l u p m u m i n i m e v i t c a t e s e r 0 0 3s n t t s r r m d o t w o l # r m m o r f y a l e d w o l # t e s e r 0 0 2s n ac operating characteristics ( over recommended operating conditions; voltages are relative to gnd )
6 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information pin descriptions v 0 , v 1 , v 2 , v 3 (16, 2, 3, 14) these inputs are used as the voltage monitor inputs and as the voltage supply for the sms46. internally they are actively diode ored and the input with the highest voltage potential will be the default supply voltage (vdd_cap). the reset# outputs will be valid if any one of the four inputs is above 1v. however, for full device operation at least one of the inputs must be at 2.7v or higher. the sensing threshold for each input is independently programmable in 5mv increments from 0.6v to 1.875v or 15mv increments from 1.8v to 5.625v. also, the occur- rence of an under- or over-voltage condition that is detected as a result of the threshold setting can be used to generate a reset#0-3. the programmable nature of the threshold voltage eliminates the need for external voltage divider networks. gnd power supply return. mr# (1) the manual reset input always generates a reset#0-3 output whenever it is driven low. the duration of the reset# output pulse will be initiated when mr# goes low and it will stay low for the duration of mr# low pulse plus the programmed reset time-out period (t prto ). mr# must be held low during a configuration register write or read. this signal is pulled up internally through a 50k ? resistor. reset#0-3 (11, 4, 5, 13) the reset outputs are active low open drain outputs. they are driven low whenever the mr# input is low or whenever a triggering under-voltage or over-voltage condition exists on the corresponding input channel or when the watchdog timer expires. the four voltage monitor inputs are always functioning, but their ability to generate a reset is program- mable ( configuration register 4 ). refer to figures 2, 3 and 5 for a detailed illustration of the relationship between mr#, reset#0-3 and the v in levels. figure 2 - reset# timing with mr# vdd_cap (12) the vdd_cap pin connects to the internal supply voltage for the sms46. a capacitor is placed on this pin to filter supply noise as well as hold up the device in the event of power failure. the voltage on this node is determined by the highest input voltage. loading of this pin should be minimized to prevent excessive power dissipation in the part. wldi (15) watchdog input. a low to high transition on the wldi input will clear the watchdog timer, effectively starting a new time-out period. this signal is pulled up internally through a 50k ? resistor. if wldi is stuck low and no low-to-high transition is received within the programmed t pwdto period (programmed watch dog time-out) the reset#0-3 outputs will be driven low. holding wldi high will not block the watchdog from timing out and generating a reset. refer to figure 4 for a detailed illustration of the relationship between reset#0-3 and wldi. a1, a2 (6, 7) a1 and a2 are the address inputs. when addressing the sms46 memory or configuration registers the address inputs distinguish which one of four possible devices sharing the common bus is being addressed. sda (9) sda is the serial data input/output pin. it should be tied to v dd_cap through a pull-up resistor. figure 3 - reset# timing mr# reset# t dmrrst t prto reset# t prto v 0 ? v 3 t drst v pth-uv
7 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information scl (10) scl is the serial clock input. it should be tied to v dd_cap through a pull-up resistor. figure 4 - watchdog and wldi timing t prto 2047 fig04 3.0 reset# wldi t 0 t 0 t 0 t 0 t 0 t prto t pwdto t pwdto figure 5 - v 0-1 inputs and resulting reset# behavior with v 0 set to uv and v 1 set to ov sensing. v 0 v pth-uv reset#0 t drst v 1 v pth-ov reset#1 t prto t drst t prto pin descriptions (continued)
8 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information table 2. configuration register 4 device operation and configuration registers supply and monitor functions the v 0 , v 1 , v 2, and v 3 inputs are internally ored so that any one of the four can act as the device supply. the reset# outputs will be guaranteed true so long as one of the four pins is at or above 1v. note : for performing a memory operation (read or write) and to have the ability to change configuration register contents at least one sup- ply input must be above 2.7v. read/write operations require a 0.1f capacitor from the vdd_cap node to gnd. for optimum performance connect capacitors from each of the vx inputs to gnd. locate the capacitors as physically close to the sms46 as possible. associated with each input is a comparator with a program- mable threshold for detection of under-voltage or over- voltage conditions on any of the four supply inputs. the threshold can be programmed in 5mv increments any- where within the range of 0.6v to 1.875v or 15mv incre- ments within the range of 1.8v to 5.625v. configuration registers 0, 1, 2, and 3 adjust the thresholds for v 0 , v 1 , v 2, and v 3 respectively. if the value contained in any register is all zeroes, the corresponding threshold will be 0.6v. if the contents were low range 05 hex the threshold would then be 0.625v [0.6v + (5 0.005v)]. all four registers are configured as 8-bit registers. table 1. configuration registers 0, 1, 2, and 3 reset# function each reset# output has a programmable source for activation. configuration register 4 is used for enabling the activation source. a monitor input can be programmed to activate on either an under-voltage or over-voltage condi- tion, but not both conditions. when this condition ceases, each individual reset# output will remain active for t prto (programmable reset time-out). the reset threshold voltage range for v0 to v3 can be set for 5mv increments below 1.875v (low range = "0") or for 15mv increments above 1.8v (high range = "1") using bits d3:0. the reset#0-3 outputs have two hardwired sources for activation: the mr# input and watchdog timer. all reset# outputs will remain active so long as mr# is low, and will continue driving the reset# outputs for t prto (programmable reset time out) after mr# returns high. the mr# input cannot be bypassed or disabled. refer to figures 1, 2 and 3 for a detailed illustration of the relationships among the affected signals. the sms46 provides the option of the monitors triggering on either an under-voltage or over-voltage condition. the low-order four bits of configuration register 5 program these options. watchdog timer the sms46 contains an independent timer that can be programmed. the watchdog generates all reset#s if it times out. the timer is cleared by a low to high transition on wldi and will reset all four reset#. if the watchdog should time-out the device status can be monitored in the status register (table 4). refer to figure 3 which illustrates the action of reset#0-3 with respect to the watchdog timer and the wldi input. 7 d b s m 6 d5 d4 d3 d2 d1 d 0 d b s l n o i t c a v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 e l b a n e r e g g i r t t e s e r e g n a r d l o h s e r h t e g a t l o v t c e l e s 0000 w o l e g n a r 1111 h g i h e g n a r 7 d b s m 6 d5 d4 d3 d2 d1 d 0 d b s l n o i t c a 11111111 v 5 2 6 . 5 = t n e m t s u j d a d l o h s e r h t t s e h g i h ) e g n a r h g i h ( 00000000 v 6 . 0 = t n e m t s u j d a d l o h s e r h t t s e w o l ) e g n a r w o l ( 00000 110 6 ( + v 6 . 0 = d l o h s e r h t v 5 2 6 . 0 = ) v 5 0 0 . 0 ) . g . e (
9 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information table 5. configuration register 6 (d3 through d7) note 1 - read only bit d7 is set to a 1. read only bits d4 and d3 are revision control and the value indi- cates the status code of the device (ie. 01 is status code 1). table 4. status register 5 (d4 through d7) table 3. configuration register 5 (d0 through d3) if wldi is held low the timer will free-run generating a series of resets. when reset# returns high (after t prto ) the timer is reset to time zero. register 6 is also used to set the programmable reset time-out period (t prto ). table 6. configuration register 6 (d0, d1, d2) n o i t c a 3 d b s m 2 d1 d 0 d b s l v 3 v 2 v 1 v 0 s e l b a n e 0 a g n i t i r w r o f n o i t c e t e d e g a t l o v r e d n u t u p n i v d e t c e l e s e h t 0000 s e l b a n e 1 a g n i t i r w r o f n o i t c e t e d e g a t l o v r e v o t u p n i v d e t c e l e s e h t 1111 2 d1 d 0 d b s l n o i t c a2 d w1 d w0 d w f f o 000 s m 0 0 4011 s m 0 0 8100 s m 0 0 6 1101 s m 0 0 2 3110 s m 0 0 4 6 111 7 d b s m 6 d5 d4 d3 d d a e r 1 y l n o 1 o t r0 o t r d a e r y l n o d a e r y l n o n o i t c a 10 0 xxt o t r p s m 5 2 = 10 1 xxt o t r p s m 0 5 = 110 xxt o t r p s m 0 0 1 = 111 xxt o t r p s m 0 0 2 = table 7. configuration register 7 (d7, d6) bits d5 through d0 are not used. 7 d b s m 6 d n o i t c a s s e r d d a t c e l e s k c o l0 s a x 0 n e h w y l n o s d n o p s e r , 0 1 0 1 = i t d s e t a t s c i g o l 1 a & 2 a = s t i b s s e r d d a x 1 n e h w y l n o s d n o p s e r , 1 1 0 1 = i t d s e t a t s c i g o l 1 a & 2 a = s t i b s s e r d d a 0 xd e l b a n e e t i r w / d a e r . g e r . g i f n o c 1 xt u o d e k c o l e t i r w / d a e r . g e r . g i f n o c note 1 - setting this bit will cause a permanent read/write lock out. 1 7 d b s m 6 d5 d 4 d b s l n o i t c a v 3 v 2 v 1 v 0 0000 e h t s e t a c i d n i 1 a g n i d a e r t l u a f t i m i l f o t u o f o e c r u o s 1111 device operation and configuration registers (continued)
10 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information smx3200 programmer the end user can use the summit smx3200 programming cable and software that have been developed to operate with a standard personal computer. the programming cable interfaces directly between a pc?s parallel port and the target application. the application?s values are entered via an intuitive graphical user interface employing drop- down menus. the latest revisions of all software and an application brief describing the smx3200 is available from the website (www.summitmicro.com). development hardware & software the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the sms46 via the programming dongle and cable. an example of the connection interface is shown in figure 6. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper device operation in the end application. figure 6 - smx3200 programmer i 2 c serial bus connections to program the sms46. pin 9, 5v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200 interface cable connector. 9 7 5 3 1 10 8 6 4 2 sms46 sda scl vdd_cap gnd 0.1 f mr# d1 c1 1n4148
11 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information table 8. memory operating characteristics 2047 table10 4.0 figure 7 - memory operating characteristics i 2 c interface note (1): these values are guaranteed by design. memory operation data for the configuration registers and the memory array are read and written via an industry standard two-wire interface. the bus was designed for two-way, two-line serial communication between different integrated cir- cuits. the two lines are a serial data line (sda) and a serial clock line (scl). the sda line must be connected to a positive supply by a pull-up resistor, located some- where on the bus. see memory operating characteris- tics: table 8 and figure 7. input data protocol the protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. the device controlling data transmission is called the master and the controlled device is called the slave. in all cases the sms46 will be a slave device, since it never initiates any data transfers. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time because changes on the data line while scl is high will be interpreted as start or stop condition. t f t r t low t high t hd:sta t su:sta t buf t dh t hd:dat t su:dat t su:sto scl sda in sda out t aa 2047 fig09 l o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u f l c s y c n e u q e r f k c o l c l c s 00 0 1z h k t w o l d o i r e p w o l k c o l c 7 . 4s t h g i h d o i r e p h g i h k c o l c 0 . 4s t f u b ) 1 ( e m i t e e r f s u bn o i s s i m s n a r t w e n e r o f e b7 . 4s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s 7 . 4s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s 0 . 4s t o t s : u s e m i t p u t e s n o i t i d n o c p o t s 7 . 4s t a a t u p t u o d i l a v o t e g d e k c o l c) n e l c y c ( a d s d i l a v o t w o l l c s2 . 05 . 3s t h d e m i t d l o h t u o a t a de g n a h c a d s o t ) 1 + n e l c y c ( w o l l c s2 . 0s t r ) 1 ( e m i t e s i r a d s d n a l c s 0 0 0 1s n t f ) 1 ( e m i t l l a f a d s d n a l c s 0 0 3s n t t a d : u s e m i t p u t e s n i a t a d 0 5 2s n t t a d : d h e m i t d l o h n i a t a d 0s n i ta d s d n a l c s r e t l i f e s i o nn o i s s e r p p u s e s i o n0 0 1s n t r w e m i t e l c y c e t i r w 5s m
12 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information figure 8 - start and stop conditions table 9. slave addresses start and stop conditions when both the data and clock lines are high the bus is said to be not busy. a high-to-low transition on the data line, while the clock is high, is defined as the start condition. a low-to-high transition on the data line, while the clock is high, is defined as the stop condition. see figure 8. acknowledge (ack) acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either the master or the slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. the master will leave the sda line high (nack) when it terminates a read function. the sms46 will respond with an acknowledge after recog- nition of a start condition and its slave address byte. if both the device and a write operation are selected the sms46 will respond with an acknowledge after the receipt of each subsequent 8-bit word. in the read mode the sms46 transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowl- edge is detected and no stop condition is generated by the master, the sms46 will continue to transmit data. if a nack is detected the sms46 will terminate further data transmissions and await a stop condition before returning to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier/address. for the sms46 the default is 1010 bin . the next two bits are the bus address. the next bit (the 7th) is the msb of the memory address. read/write bit the last bit of the data stream defines the operation to be performed. when set to 1 a read operation is selected; when set to 0 a write operation is selected. write operations the sms46 allows two types of write operations: byte write and page write. a byte write operation writes a single byte during the nonvolatile write period (t wr ). the page write operation, limited to the memory array, allows up to 16 bytes in the same page to be written during t wr . byte write after the slave address is sent (to identify the slave device and select either a read or write operation), a second byte is transmitted which contains the low order 8 bit address of any one of the 512 words in the array. upon receipt of the word address the sms46 responds with an acknowledge. after receiving the next byte of data it again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the sms46 begins the internal write cycle. while the internal write cycle is in progress the sms46 inputs are disabled and the device will not respond to any requests from the master. page write (memory only) the sms46 is capable of a 16-byte page write operation. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word the master can transmit up to 15 more bytes of data. after the receipt of each byte the sms46 will respond with an acknowledge. the sms46 automatically increments the address for subsequent data words. after the receipt of each word the low order address bits are internally incremented by one. 2047 fig10 scl sda in start condition stop condition 7 d b s m 6 d5 d4 d3 d2 d1 d 0 d b s l s t i b s s e r d d a e p y t e c i v e ds u bb s mw / r 6 4 s m sxxxx 10 01 ? r e t s i g e r n o i t a r u g i f n o c 10 10 ? ) t l u a f e d ( y r o m e m 10 11 ? y r o m e m e t a n r e t l a i 2 c interface (continued)
13 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information figure 9 - read and write operations the high order bits of the address byte remain constant. should the master transmit more than 16 bytes, prior to generating the stop condition, the address counter will rollover and the previously written data will be overwrit- ten. as with the byte write operation, all inputs are disabled during the internal write cycle. refer to figure 11 for the address, acknowledge, and data transfer sequence. n a c k n a c k typical write operation (standard memory device type) s t a r t a c k b a 2 b a 1 a 8 r / w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k s t o p master sda slave 0 1 10 a c k r / w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k s t o p s t a r t writing configuration registers master sda slave 01 10 master sda slave device type address bus address a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k r / w a c k s t a r t c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 reading the configuration register 01 10 a c k r / w s t o p s t a r t d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01 10 up to 15 additional bytes can be written before issuing the stop. b a 2 b a 1 x b a 2 b a 1 x b a 2 b a 1 x 2047 fig11 typical reading operation (alternate memory device type) master sda slave a c k r / w a c k s t a r t a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 11 10 a c k r / w s t o p s t a r t d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11 10 b a 2 b a 1 a 8 b a 2 b a 1 a 8 i 2 c interface (continued)
14 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information figure 10 - write flow chart acknowledge polling when the sms46 is performing an internal write operation it will ignore any new start conditions. since the device will only return an acknowledge after it accepts the start the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. see the flow chart for the proper sequence of operations for polling. read operations read operations are initiated with the r/w bit of the identification field set to 1. there are two different read options: 1. current address byte read, and 2. random address byte read. current address read (memory only) the sms46 contains an internal address counter which maintains the address of the last word accessed, incre- mented by one. if the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. when the sms46 receives the slave address field with the r/w bit set to 1 it issues an acknowledge and transmits the 8-bit word stored at address location n+1. the current address byte read operation only accesses a single byte of data. the master sets the sda line to nack and generates a stop condition. at this point the sms46 discontinues data transmission. random address read (register and memory) random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condi- tion and the slave address field (with the r/w bit set to write), followed by the address of the word it is to read. this procedure sets the internal address counter of the sms46 to the desired address. after the word address acknowledge is received by the master it immediately reissues a start condition, followed by another slave address field with the r/w bit set to read. the sms46 will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location. at this point the master sets the sda line to nack and generates a stop condition. the sms46 discontinues data transmission and reverts to its standby power mode. sequential read (memory only) sequential reads can be initiated as either a current address read or random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read); however, the master now responds with an acknowledge, indicating that it requires additional data from the sms46. the sms46 continues to output data for each acknowl- edge received. the master terminates the sequential read operation by responding with a nack, and issues a stop condition. during a sequential read operation the internal address counter is automatically incremented with each acknowledge signal. for read operations all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address the address counter will rollover and the memory will continue to output data. next operation a write? ack returned issue address proceed with write await next command issue stop issue slave address and r/w = 0 issue stop write cycle in progress ye s no issue start 2047 fig12 ye s no i 2 c interface (continued)
15 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information applications figure 11 - application schematic notes: 1. c1 is a 0.1f. 2. connector j1 is an smx3200 (see figure 6). 3. d1 is a 1n4148 sms46 2 4 6 8 10 1 3 5 7 9 mr# v0 v1 v2 v3 wldi reset#0 reset#1 reset#2 scl sda a1 a2 gnd 1 16 2 3 14 10 9 6 7 11 4 5 13 8 j1 c1 v 0 v 1 v 2 v 3 2047 fig13 vdd_cap 12 15 reset#3 d1
16 sms46 2083 1.1 06/04/04 summit microelectronics, inc. preliminary information package 16 pin ssop package 0.007 - 0.010 (0.18 - 0.25) 0.150 - 0.157 (3.81 - 3.99) 0.025 (0.635) 0.016 - 0.050 (0.41 - 1.27) 0.008 - 0.012 (0.20 - 0.31) 0.189 - 0.197 (4.80 - 5.00) 0.228 - 0.244 (5.79 - 6.20) pin 1 0.004 - 0.010 (0.10 - 0.25) 0.059 (1.50) 0.053 - 0.069 (1.35 - 1.75) max 16 pin ssop ref. jedec mo-137 inches (millimeters) 0? min to 8? max default configuration register settings - sms46gc-238 the default device ordering number is sms46gc-238, is programmed as described above and tested over the commercial temperature range. register contents function r00 56 v0 threshold set to 3.090v r01 28 v1 threshold set to 2.400v r02 a0 v2 threshold set to 1.400v r03 14 v3 threshold set to 0.700v r04 f3 reset trigger source set for all channels, v0, v1 set to high range and v2, v3 set to low range r05 x0 upper bits are volatile status indication of input supply condition. v0, v1, v2 and v3 set to monitor uv under voltage. r06 c5 reset timeout set to 100ms, w atchdog timer set to 1.6s. bits d4 and d3 indicate revision control. r07 40 ee memory slave address is 1011, configuration registers are unlocked.
17 2083 1.1 06/04/04 sms46 summit microelectronics, inc. preliminary information notice note 1 - this is a preliminary information data sheet that describes a summit product currently in pre-production with limited characterization. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herei n, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and sche dules contained herein reflect representative operating parameters, and may vary depending upon a user?s specific application. while the inform ation in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result o f any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their sa fety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to i ts satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. r evision 1.1 - this document supersedes all previous versions. please check the summit microelectronics, inc. web site at www.summitmicro.com for data sheet updates. ? copyright 2004 summit microelectronics, inc. programmable analog for a digital world? i 2 c is a trademark of philips corporation. ordering information sms46 g nnn package g =16 lead ssop part num ber suffix (see page 17) summit part number specific requirem ents are contained in the suffix such as hex code, hex code revision, etc. c tem p range c=commercial blank=industrial sms46g ayyww pin 1 identifier annn summit part number date code (yyww) part number suffix (contains customer specific ordering requirements) lot tracking code (summit use) drawing not to scale xx status tracking code (blank, ms, es, 01, 02,...) (summit use) product tracking code (summit use) summit part marking

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